PYNQ Tutorials¶
This page is a collection of material from the PYNQ team, partners, and PYNQ users covering a range of topics related to design and development with PYNQ. You can write your own tutorials and post them to the PYNQ support forum. You can submit a pull request to the PYNQ GitHub repository linking your tutorial from this page.
PYNQ Workshop¶
The PYNQ workshop material is an introduction training workshop developed by the PYNQ team. It includes PDF presentations and hands-on exercises and is recommended for beginners. The material is based on the PYNQ-Z2 board but can be used on other PYNQ boards.
- Session 1: Introduction to using Jupiter with PYNQ
- Session 2: Introduction to using peripherals with the PYNQ base Overlay
- Session 3: Introduction to PYNQ IOPs and the logictools overlay
- Session 4: Introduction to designing overlays
Using PYNQ¶
- Introduction to Jupyter Lab running on PYNQ
- Exploring the PYNQ environment with Jupyter Lab
- Example of basic visualisation with Jupyter
- What’s in My Bitstream - A Pythonic Approach to Discovering FPGA Contents
- Example of using AXI GPIO
- Example of using MMIO
- Using Register Map
- Example of a allocating memory (the memory can be used from the programmable logic)
- FPGA data movement with NumPy
- Example of using the AXI DMA
Hardware design¶
Vivado¶
- Rebuilding the PYNQ base overlay (v2.6, PYNQ)
- Creating a new Vivado hardware design for PYNQ
- Creating a design with SPI, I2C, UART On PYNQ: A PL Approach (Makarena Labs)
- Creating a new Verilog module Overlay
- Creating a Verilog Overlay with bidirectional pins
- How to accelerate a Python function (FIR filter) with PYNQ (FPGA Developer)
Two part tutorial on using PS GPIO with PYNQ, covering the Vivado design in part 1, then using the design from PYNQ in part 2.
Two part tutorial on using a DMA with PYNQ, covering the Vivado design in part one, then using the design from PYNQ in part two.
High Speed offload using the UltraScale+ Integrated 100G Ethernet Subsystem
HLS design¶
Three part tutorial on using a HLS stream IP with DMA. Part 1 covers the HLS design, part 2 covers the Vivado design and part 3 shows how to use the design from PYNQ.
Hardware Debug¶
Building a PYNQ image¶
Software tutorials¶
- Using Docker with PYNQ
- Dynamically Creating Usable Python Objects
- Creating a PyPi package for your design
- Microsoft’s VS Code for C/C++/Python Development on Xilinx Platforms
- Continuous Integration using Jenkins and Docker: automate building PYNQ FPGA overlays and source distribution
- Interactive C++ on the Kria-SoM in Jupyter Lab